Memory Stacking

OVERVIEW

For decades, the demand from consumer products and data center applications for higher performance, higher capacity and lower cost per bit memory has driven the industry to smaller critical line-width dimensions and geometries. Multichip packages, such as Dual-Die Package (DDP) and Quad-Die Package (QDP), that allow even more memory capacity per unit area are also being used to address the problem; however, they tend to reduce overall electrical and thermal performance.
3D DRAM delivers compelling benefits in terms of performance and power consumption when compared to conventional DRAM; however, wide-scale market adoption has been limited, due to cost and manufacturing complexity. This trade-off between performance, capacity and cost is likely to become even more challenging as the industry rapidly approaches the limits of Moore’s Law.
Invensas offers multiple innovative and cost-effective memory stacking solutions that address the performance limitations of DDP and QDP, and the cost issues and manufacturing complexity of 3D DRAM.

TECHNOLOGIES

DBI® Ultra is an enabling low-temperature, low profile die to wafer and die to die hybrid bonding technology platform. By eliminating the need for copper pillars and underfill, DBI Ultra can enable a dramatically thinner stack than conventional approaches.  DBI Ultra also allows the stacking of die that are the same or different sizes, processed on fine or coarse wafer process technology nodes, or manufactured on the same or different wafer sizes while readily scaling down to 1 µm interconnect pitch providing the ultimate 2.5D and 3D integration flexibility.

DIFFERENTIATORS

DBI-Ultra_Differentiators

Lower latency

Lower manufacturing and implementation cost

Better thermal performance

Enhanced electrical and thermal performance

Thinner 3D stacking

MARKETS

Invensas memory stacking solutions increase memory capacity in Consumer and Data Center markets while satisfying performance and cost constraints.

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